(a) Field of the Invention
The present invention relates to a method for manufacturing a thin film transistor (TFT) array panel for a liquid crystal display (LCD).
(b) Description of the Related Art
Thin film transistors used for an LCD have two different types of structure. One is an etch-back type and the other is an etch-stopper type.
When manufacturing an etch-back type TFT, an amorphous silicon layer and a doped amorphous silicon layer are deposited in sequence and patterned. Next, a metal layer is deposited and patterned to form a data wire including source and drain electrodes, and the doped amorphous silicon layer is etched by using the source and the drain electrodes as etching mask. In the etch stopper type TFT, an etch stopper, which has a large etch selectivity, is formed between an amorphous silicon layer and a doped amorphous silicon layer.
Now, a conventional method for manufacturing a TFT array panel for an LCD will be described with reference to the FIGS. 1A to 1D.
FIGS. 1A to 1D are cross-sectional views of a TFT array panel, as it undergoes sequential processing steps according to the conventional manufacturing method.
First, as shown in FIG. 1A, an aluminum-neodymium (Al--Nd) layer 11 and a molybdenum (Mo) layer 12 are sequentially deposited on a substrate 1 and patterned to form a gate electrode 10. That is, a gate wire having the gate electrode 10 is formed. A gate insulating layer 13, an amorphous silicon layer 14 and an n+ amorphous silicon layer 15 are sequentially deposited over the gate electrode 10.
Next, as shown in FIG. 1B, the amorphous silicon layer 14 and the n+ amorphous silicon layer 15 are patterned to form a semiconductor pattern. Subsequently, with reference to FIG. 1C, a metal layer is deposited on the n+ amorphous silicon layer 15 and patterned to form a source electrode 16 and a drain electrode 17. Before the deposition of the metal layer, a natural oxide layer (not shown) formed on the n+ amorphous silicon layer 15 is removed by a wet etch cleaning process using hydrogen fluoride (HF). Accordingly, the contact resistance between the n+ amorphous silicon layer 15 and both the source electrode 16 and the drain electrode 17 is reduced. After forming the source electrode 16 and the drain electrode 17, an exposed portion of the n+ amorphous silicon layer 15 is etched using the source and drain electrode 16 and 17 as mask.
As shown in FIG. 1D, a passivation layer 18 is deposited and patterned to have a contact hole 19 exposing the drain electrode 17. Finally, an indium tin oxide (ITO) layer is deposited and patterned to form a pixel electrode 20.
However, the conventional method for manufacturing a TFT array panel has many problems.
Impurities, which are generated during semiconductor patterning and HF cleaning processes, may remain on the n+ amorphous silicon layer 15, and cause disconnections of the source electrode 16 and the drain electrode 17. Further, even with HF cleaning, portions of the natural oxide layer remain. The remaining natural oxide coupled with the impurities, degrades an ohmic contact between the n+ amorphous silicon layer 15 and both the source electrode 16 and the drain electrode 17, thereby reducing the on current (Ion) of the TFT. Furthermore, pixel electrodes 20 adjacent to a data line (not shown) interposed therebetween, may be short-circuited when forming the pixel electrodes 20 due to the ITO residues between the pixel electrodes 20. Finally, a photomask misalignment occurring in the photolithography process of forming the amorphous silicon layer 14 may result in stitch defects because the parasitic electrostatic capacitance (Cgd) between the gate electrode 10 and the drain electrode 17 becomes different depending on each photo shot.